2nd Workshop on Hardware/Software Techniques for Minimizing Data Movement (Min-Move 2018) @ ASPLOS 2018


Final Workshop Program

Time Workshop Agenda (March 24th, 2018) Speaker/Authors Material
08:30AM - 08:40AM   Welcome and Introductions   Adwait Jog (William & Mary) and EJ Kim (Texas A&M University)   (Slides, PPTX)  
08:40AM - 09:30AM   Keynote 1: Untrodden Paths for Near Data Processing   Rajeev Balasubramonian (Univ. of Utah)   (Slides, PPTX)  
09:30AM - 10:00AM   An Extensible Scheduler for the OpenLambda FaaS Platform   Gustavo Totoy, Edwin Boza, and Cristina Abad (ESPOL, Ecuador)   (Paper)  
10:00AM - 10:30AM   Coffee Break      
10:30AM - 11:20AM   Keynote 2: In-Memory Automata Processing   Reetuparna Das (Univ. of Michigan)   (Slides, PDF)  
11:20PM - 12:10PM   Keynote 3: Designing large scale systems with a data-centric approach   Alessandro Morari (IBM)   (Slides, TBD)  
12:10PM - 12:15PM   Wrap-up   Adwait Jog (William & Mary) and EJ Kim (Texas A&M University)    

Keynote 1

Speaker: Rajeev Balasubramonian, Utah

Title: Untrodden Paths for Near Data Processing

Abstract: Near Data Processing (NDP) can unlock large savings in data movement costs. While much of the initial NDP spotlight has focused on 3D-stacked memory+logic devices, in this talk, we highlight other opportunities that deserve more attention: (i) accelerators that leverage in-situ computing, (ii) feature-rich DIMMs that serve as cheap alternatives to 3D-stacked devices, and (iii) near-data implementations of privacy and security features.

Bio: Rajeev Balasubramonian is a Professor at the School of Computing, University of Utah. He received his Ph.D. in 2003 from the University of Rochester. His primary research interests include memory systems, security, and application-specific architectures. Prof. Balasubramonian is a recipient of an NSF CAREER award, an IBM Faculty Partnership award, an HP IRP award, an Intel Outstanding Research Award, and various teaching awards at the University of Utah. He has co-authored papers that have received three best paper awards and two IEEE Micro Top Picks.

Keynote 2

Speaker: Reetuparna Das, UMich

Title: In-Memory Automata Processing

Abstract: Finite State Automata is widely used to accelerate pattern matching in many emerging application domains. Conventional CPUs and compute-centric accelerators are bottlenecked by memory bandwidth and irregular memory access patterns in automata processing. In this talk, I will present a new hardware design that allows automata which are known to be embarrassing sequential, to be executed in parallel in DRAM-based in-memory accelerator. I will also present Cache Automaton, which repurposes conventional last-level cache architecture for automata processing.

Bio: Reetuparna Das is an Assistant Professor at U. Michigan. Prior to this, she was a research scientist at Intel Labs, and the researcher-in-residence for the C-FAR center. She is an expert in computer architecture. She has authored over 45 papers, and filed 7 patents. She has an IEEE Top Picks award, an NSF CAREER award, and IEEE/ACM MICRO Hall of Fame award. Her recent work on in-memory design named Compute Caches received the best Demo award in C-FAR. She also serves as the CEO of a precision medicine start-up, Sequal Inc.

Keynote 3

Speaker: Alessandro Morari, IBM

Title: Designing large scale systems with a data-centric approach

Abstract: Current hardware trends clearly indicate that data is a first-class citizen when talking about scalable system performance. The reduction of data movements and the centrality of data to system design is a key principle of the data-centric system approach. In this talk, I will discuss what are the opportunities as we move from a compute-centric to a data-centric system design, and how this can be implemented in the entire hardware-software stack. I will talk about our experience with reducing data movement on a large scalable system such as the IBM CORAL Supercomputer and about the challenges that lies in front of us to the achievement of an Exascale machine.

Bio: Alessandro Morari leads the System Software team in the Data Centric Systems department at IBM Research. This team performs research and development of software at the intersection between traditional high performance computing and next generation data-centric systems. He has published extensively in international conferences and journals, and he is currently involved in several governmental and academic projects. He and his team have also been involved in the development of system software for the IBM CORAL Supercomputer commissioned by the US Department of Energy.

Previous Version


The goal of achieving exascale performance under stringent power budget is important, exciting, and challenging. One of the biggest impediments in achieving this goal is the excessive data movement across different levels of the memory hierarchy. In this workshop, we intend to discuss innovative ways to reduce this data movement in a variety of architectures (including CPUs, GPUs, handhelds, data centers, IoT, accelerators etc.). We welcome all novel submissions that describe hardware, software, or hardware-software co-design techniques to reduce the data movement.


Any idea/technique that can help in reducing the data movement is appropriate for this workshop. Some topics (but not limited to) are:



An on-line version of all the papers will be available on the workshop website. This choice allows authors to use feedback from the workshop to extend their work for future publication.

Important Dates

Program Committee